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| PUCC3801 Current-mode PWM controller Rev. 01 -- 10 September 2001 Product data 1. General description The PUCC3801 is a current-mode Pulse Width Modulated (PWM) controller containing all the control and protection functions necessary to implement an off-line, flyback or forward converter with a minimum number of external components. 2. Features s Very low start-up supply current; 50 A typical s Low operating supply current; 1.2 mA typical s Accurate, internally-trimmed, fixed frequency oscillator (100 kHz). No external timing components needed s Internal slope compensation. No external ramp components needed s Built-in over-voltage and under-voltage detection s High-speed over-current trip; 170 ns typical s Over-voltage clamp on supply voltage (VDD) s Internal divider regulates VDD to 12 V. No external divider needed s Leading edge blanking of the current sense signal s Control frequency modulated over a narrow band to reduce Electromagnetic Interference (EMI) s High output drive capability; 150 ns typical rise and fall time into 2 nF load s Wide bandwidth (10 MHz) error amplifier with external compensation pin and simple interface to optocoupler s Accurate internal bandgap reference. 3. Applications s Off-line switched mode power supplies s Laptop computer mains adaptors s Printer power supplies. Philips Semiconductors PUCC3801 Current-mode PWM controller 4. Ordering information Table 1: Ordering information Package Name PUCC3801P PUCC3801T DIP8 SO8 Description plastic dual in-line package; 8 leads (300 mil) plastic small outline package; 8 leads; body width 3.9 mm Version SOT97-1 SOT96-1 Type number 5. Block diagram VDD 7 VDD VDD(comp) lev5V CHIPON lev8V VREG 8 REG lev10V POR lev14V lev5V to all sections VCC OV LATCH lev14V 5 A Z1 8 k to overcurrent comparator to OSC, DRIVER, PWM 4 OSC RANDOM slope compensation ramp VDD n.c. POWER MANAGER Bandgap 1.25 V Z2 1 VCC COMP ERRAMP osc DRIVER FB 2 PWM REF 2.5 V x 0.4 6 OUT 5 A 3 Bandgap 1.25 V shutdown PGND 5 CSNS OVERCURRENT COMPARATOR GND PUCC3801 03af30 Fig 1. Block diagram. 9397 750 08419 (c) Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 -- 10 September 2001 2 of 16 Philips Semiconductors PUCC3801 Current-mode PWM controller 6. Pinning information 6.1 Pinning COMP 1 FB 2 8 REG 7 VDD 6 OUT 5 GND 03af31 COMP 1 FB 2 8 REG 7 VDD 6 OUT 5 GND 003aaa119 PUCC3801P CSNS 3 n.c. 4 PUCC3801T CSNS 3 n.c. 4 Fig 2. Pin configuration; PUCC3801P (SOT97-1). Fig 3. Pin configuration; PUCC3801T (SOT96-1). 6.2 Pin description Table 2: Symbol COMP FB CSNS n.c. GND OUT VDD REG Pin description Pin 1 2 3 4 5 6 7 8 I/O I/O I I - - O - O Description compensation pin feedback pin current sense input no connection circuit common ground gate drive output positive supply voltage voltage regulator decoupling pin 7. Functional description 7.1 Pin functions 7.1.1 Compensation pin (COMP) The compensation pin is connected to the output of the error amplifier (ERRAMP). This pin is normally connected via a feedback network to the FB pin. The COMP pin can also be used as an input for an optocoupled control signal to the pulse width modulator (PWM) comparator. When an optocoupler is used, the collector of the optocoupler photo-transistor is connected to the COMP pin, with a pull-up resistor to VDD. The FB pin must be grounded to force the output of the error amplifier HIGH. 7.1.2 Feedback pin (FB) The feedback (FB) pin is the inverting input to the error amplifier. If FB is left open, an internal divider from VDD will tend to regulate VDD at a nominal 12 V. 9397 750 08419 (c) Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 -- 10 September 2001 3 of 16 Philips Semiconductors PUCC3801 Current-mode PWM controller 7.1.3 Current sense input pin (CSNS) The signal on the current sense input pin is connected to the input of the pulse width modulator comparator. A low pass filter suppresses transients and noise on the leading edge of the current sense signal. Inside the PWM, a slope compensation ramp, derived from the main oscillator (OSC) is added to the current sense signal. The internal slope compensation feature allows stable operation of the converter at duty cycles greater than 50%. The signal on the current sense input pin is also connected to the input of an over-current comparator. If the amplitude of the current sense signal exceeds 1.25 V, the comparator detects an overload condition and immediately terminates the output pulse. The propagation delay from CSNS to output, in an over-current condition, is typically 170 ns. 7.1.4 Common circuit ground pin (GND) This is the common power and signal ground connection. The power and signal grounds are separated internally for improved noise immunity. 7.1.5 Gate drive output pin (OUT) When no output pulses are being produced, this pin is held LOW. An external pull-down resistor on the MOSFET gate is not required. 7.1.6 Positive supply voltage pin (VDD) An internal shunt regulator allows the device to be powered via a resistor from a widely varying supply. The device power management section keeps the device in start-up current mode whilst VDD is ramping up. When the supply voltage reaches the start-up threshold, the device turns on and draws the specified supply current. If VDD drops below the under-voltage lockout threshold, the device returns to start-up current mode. 7.1.7 Voltage regulator pin (REG) This is a decoupling pin for the internal low voltage supply (VREG). This pin must not be loaded during start-up or whilst the device is in start-up current mode. 7.2 Device sections The device can be considered as two sections (see Figure 1): * Power-up section consisting of the POWER MANAGER, VREG, VCC, OV LATCH and VDD(comp) circuitry. This part is always active. * Controller section consisting of the ERRAMP, PWM, DRIVER, OSC, RANDOM and OVERCURRENT COMPARATOR. This part is supplied by an internally generated 5 V supply (VCC), controlled by the power-up section. The controller section is kept switched off during power-up to minimize the start-up current. 7.2.1 Power-up section Power-up sequence: The power-up sequence disables the controller section and keeps the start-up current below 70 A until VDD rises above 10 V. 9397 750 08419 (c) Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 -- 10 September 2001 4 of 16 Philips Semiconductors PUCC3801 Current-mode PWM controller With reference to Figure 4, assume that VDD is rising slowly from zero to 12 V. The Power Manager produces a Power-On Reset (POR) signal that is routed to every flip-flop and counter in the device. This signal is made active as early as possible in the power-up sequence to ensure that the internal logic is reset and the device powers up in a known state. The POR remains active until the bandgap reference voltage (Vbandgap) stabilizes and the comparators in the power manager block have all settled into stable states. The POR signal is then released and, once the supply voltage, VDD reaches 10 V, the controller section is enabled and the device starts to produce output pulses. VDD (V) 12.0 10.0 VDD 4.0 -2.0 03af32 6.0 POR 5.0 VREG VDD(comp) (V) 2.0 -1.0 3.0 2.5 Vbandgap (V) 1.0 -0.5 VDD(comp) VREG POR V bandgap 0 50 100 150 time 200 250 (s) 300 Fig 4. Power-up sequence. Over-voltage and under-voltage functions: Figure 5 shows the over-voltage trip sequence. 1.2mA IDD 70 A 70 A 1.2mA VOUT 14 V VDD 10 V 5V VREG = 6 V (on) 3V 03af33 regulated VDD = 12V 10 V 6V VREG VREG = 3 V (off) Fig 5. Over-voltage and under-voltage functions. A coarse internal supply VREG is generated by the VREG section. In standby mode, this supply drops to a low level, typically 3 V, and the current into the VDD pin is limited to a low value, less than 70 A. 9397 750 08419 (c) Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 -- 10 September 2001 5 of 16 Philips Semiconductors PUCC3801 Current-mode PWM controller When VDD rises above 10 V, VREG rises to 6 V and the operating supply current increases to typically 1.2 mA. The device starts normal operation and output pulses are produced. The over-voltage trip sequence is initiated if VDD rises above 14 V. When this happens, the output pulses are disabled, VREG is reduced gradually to 3 V, and the output of the over-voltage latch goes HIGH. The device remains in the over-voltage lockout mode until VDD falls below 5 V. Input voltage clamp: VDD is clamped to a maximum of 16.5 V. The size of the external resistor must be sufficient to ensure that the current into the VDD pin never exceeds 15 mA. 7.2.2 Controller section Oscillator: The internal oscillator generates a 75% duty cycle digital clock to the output latch, and a 100 kHz voltage ramp to the PWM circuit. The frequency is modulated by approximately 20% by a Pseudo Random Binary Sequence (PRBS) that repeats every 15 cycles. This spreads the electromagnetic interference produced by the power supply over a narrow band of frequencies centered on 100 kHz. This reduces the amplitude of the harmonics in the interference spectrum. Error amplifier: This section senses one of the various feedback methods used to control the output duty cycle. It contains an operational transconductance amplifier (ERRAMP), that can be externally compensated at the COMP pin. The reference input of ERRAMP is connected to a 2.5 V reference voltage. The FB input is internally connected to a voltage divider from VDD. If the FB pin is not connected, the device will tend to regulate VDD to 12 V. The output of the error amplifier is connected to the PWM section by a voltage divider with a gain of 0.4 and an output impedance of 100 k. PWM: The PWM section includes a current sense input from the CSNS pin, a low-pass filter, summing amplifier, a high-speed comparator and logic. This section sums the analog ramp from the oscillator with the voltage on the CSNS pin. This signal is fed to a comparator that triggers on the falling edge of the PWM clock signal. This provides line compensation and load regulation. The internal slope compensation function removes the need for external components to generate a ramp signal that is added to the current sense signal. A fast over-current path is provided from CSNS to OUT with a typical propagation delay of 170 ns. Output driver: This section is a high-speed, high-current output stage capable of driving the gate of a large power FET. Typical rise and fall times are 160 ns and 150 ns respectively into a 2 nF load. 9397 750 08419 (c) Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 -- 10 September 2001 6 of 16 Philips Semiconductors PUCC3801 Current-mode PWM controller 8. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VCOMP VFB IDD IORM IREG ICOMP Ptot Parameter supply voltage voltage on COMP pin voltage on FB pin supply current into VDD pin repetitive peak output current current out of REG pin current into COMP pin total power dissipation PUCC3801P PUCC3801T Tj Tstg Tsp junction temperature storage temperature solder point temperature non-operating during soldering; t 10 s - - 0 -60 - 0.5 0.3 105 +150 300 W W C C C Conditions IDD 15 mA low impedance source Min - - -0.3 -0.3 - - - - Max 15 13 Unit V V VREG + 0.3 V VREG + 0.3 V 15 0.6 10 1 mA A mA mA 9. Characteristics Table 4: Characteristics VDD = 12 V; CSNS = LOW; Cload = 2000 pF; CREG = 100 nF (REG to GND); Tamb = 0 to 105 C; unless otherwise specified. Symbol IDD(su) IDD(oper) Parameter start-up supply current into VDD pin Conditions VDD 9 V Min 20 0.5 Typ 50 1.2 Max 70 4 Unit A mA Supply current operating supply current into VDD VDD = 12 V; no load pin on other pins start-up threshold voltage under-voltage threshold voltage over-voltage threshold voltage VDD increasing; VREG > 5 V VDD decreasing; VREG < 5 V VDD increasing; OV latch output = HIGH VDD decreasing; OV latch output = LOW Supply voltage and over-voltage function VDD(th)su VDD(th)uv VDD(th)ov 9 7.6 13 10 8 14.2 11 8.4 14.7 V V V - 5 - V Vhys VDD(clamp) hysteresis clamping voltage IDD = 10 mA; no load on other pins - 13 2 14.8 - 16.5 V V 9397 750 08419 (c) Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 -- 10 September 2001 7 of 16 Philips Semiconductors PUCC3801 Current-mode PWM controller Table 4: Characteristics...continued VDD = 12 V; CSNS = LOW; Cload = 2000 pF; CREG = 100 nF (REG to GND); Tamb = 0 to 105 C; unless otherwise specified. Symbol VREG Parameter regulator voltage Conditions IREG = -1 mA IREG = -5 mA; VDD = 7.6 V IREG = -10 mA; VDD = 7.6 V over-voltage condition Vbandgap Oscillator TAV(osc) Nrep T ( osc ) -------------------T AV ( osc ) Min 5.5 5 4.5 2.8 - [1] Typ 5.7 5.4 5.0 3.2 1.25 10.0 15 20 75 - Max 7 - - 4.4 - 10.7 - 23 80 - Unit V V V V V s cycles % % ns Low voltage regulator bandgap voltage average period modulation repetition number of cycles modulation (peak-to-peak value) maximum duty factor minimum pulse duration IREG = -1 mA 8.4 V < VDD < 13 V; 15 cycle average 9.3 - 17 70 500 [1] [1] max tW(min) VCOMP = 4 V VCSNS = 0 V; VCOMP = slope compensation stop voltage VCOMP = 12 V; FB connected to COMP from FB pin to GND FB pin open no load on COMP pin no load on COMP pin VFB = 2 V VFB = 3 V VCOMP = 3 V; VFB = 2 V VCOMP = 1 V; VFB = 3 V [1] [1] Error amplifier Vi(ref)(FB) Ri(FB) VDD(reg) Gol GB VOH(COMP) VOL(COMP) IO(source) IO(sink) non-inverting input reference voltage input resistance at FB pin VDD regulation voltage open-loop gain gain bandwidth product HIGH-level output voltage at COMP pin LOW-level output voltage at COMP pin output source current out of COMP pin output sink current into COMP pin [2] 2.37 - 11.4 65 - 4.5 - -100 125 2.5 100 12 75 10 5.1 65 -50 300 2.62 - 12.6 85 - - 250 -25 500 V k V dB MHz V mV A A 9397 750 08419 (c) Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 -- 10 September 2001 8 of 16 Philips Semiconductors PUCC3801 Current-mode PWM controller Table 4: Characteristics...continued VDD = 12 V; CSNS = LOW; Cload = 2000 pF; CREG = 100 nF (REG to GND); Tamb = 0 to 105 C; unless otherwise specified. Symbol Parameter scaling of CSNS voltage to COMP voltage input impedance at CSNS pin input filter time constant propagation delay from CSNS to VCOMP = 1.4 V; OUT via PWM VCSNS = 1V pulsed slope compensation start voltage VCSNS = 0 V; duty cycle = maximum slope compensation stop voltage VCSNS = 0 V; no output pulses comparator threshold voltage at CSNS pin VFB = 2 V [6] [4] Conditions [3] Min - - - - 2.2 0.3 Typ 40 100 320 300 2.4 0.5 Max - - - - 2.6 0.6 Unit % k ns ns V V Current sense comparator V CSNS ----------------V COMP Zi(CSNS) filter tPD(PWM) VSC(start) VSC(stop) fin = 1 MHz [5] [5] Over-current sense comparator Vth(CSNS) tPD(OC) - - 1.25 170 - 250 V ns propagation delay from CSNS to VCOMP = 4 V; OUT via over-current comparator VCSNS = 1.65 V; pulsed LOW level output voltage HIGH-level output voltage HIGH-level output resistance LOW-level output resistance output rise time output fall time IOUT = 10 mA VDD = 12 V VDD = 12 V; IOUT = 10 mA VDD = 12 V; IOUT = 10 mA CL = 2 nF; 10% to 90% CL = 2 nF; 90% to 10% Output VOL VOH ROH ROL to(r) to(f) - - 30 1 [7] 0.06 VDD 65 7 160 150 1.7 - 90 14 260 250 V V ns ns 60 50 [7] [1] [2] [3] [4] [5] [6] [7] Measured at OUT pin. Measured at COMP pin. The amplifier output is connected to the PWM section by a voltage divider with a gain of 0.4 and an impedance of 100 k. The propagation delay is measured from the 50% point on the CSNS input voltage to the 90% point on the falling edge of the output pulse. A HIGH of 1 V is generated on CSNS after every rising edge of VOUT. With CSNS tied to ground, the duty cycle can be controlled by varying the voltage on COMP. VSC(start) is the voltage on COMP that produces maximum duty cycle. VSC(stop) is the voltage on COMP at which the output pulses disappear. The propagation delay is measured from the 50% point on the CSNS input voltage to the 90% point on the falling edge of the output pulse. A HIGH of 1.65 V is generated on CSNS after every rising edge of VOUT. These limits are not guaranteed. The values are based on simulation results only. 9397 750 08419 (c) Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 -- 10 September 2001 9 of 16 Philips Semiconductors PUCC3801 Current-mode PWM controller 10. Application information 10.1 Off-line flyback regulator 4.7 (1 W) 4x 1N4007 220 F (400 V) 1 M (0.25 W) BZD142W-68 (ZENBLOCK) Np T1 BYV27-100 Ns 4700 F (10 V) DC output 5 V/5 A + BYV27-100 10 F (16 V) - AC input 80 - 270 Vrms Nf 1 F (10 V) Note T1: Lp = 240 H Np : Ns = 22.3 Np : Nf = 10.0 PHP1N60R COMP 1 8 7 REG VDD OUT GND FB 2 CSNS n.c. 3 4 PUCC3801 6 5 1 03af34 Fig 6. Off-line flyback regulator. Figure 6 shows a typical application diagram of a low-cost, off-line, flyback regulator. The circuit uses a minimum number of external components. The PUCC3801 has an internal voltage divider from VDD. When the FB pin is left open circuit, the circuit regulates VDD at 12 V. Load regulation is dependent upon close coupling between the secondary and feedback windings, and the leakage inductance of the transformer. The circuit is designed to operate over the input voltage range 90 - 270 V (RMS). The low start-up current of the PUCC3801 means that the dissipation in the 1 M, 0.25 W resistor to VDD does not become excessive at high input voltages. The internal slope compensation allows stable operation at low input voltage and maximum load where the duty cycle is greater than 50%. 10.2 Optocoupler interface BYV27-100 4700 F (10 V) isolated secondary 4.7 k 180 100 nF 4.7 k DC output primary side 12 V COMP FB CSNS n.c. 1 2 3 4 8 7 REG VDD OUT GND PUCC3801 6 5 TL431 4.7 k 03af35 Fig 7. Optocoupler interface to PUCC3801. 9397 750 08419 (c) Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 -- 10 September 2001 10 of 16 Philips Semiconductors PUCC3801 Current-mode PWM controller Figure 7 shows the method of interfacing an optocoupler to the PUCC3801. The error amplifier is overridden by holding the FB pin LOW. This causes the output of the error amplifier to go HIGH. In this state, the amplifier sources a constant current of typically 50 A into the collector of the optocoupler. The pull-up resistor to VDD sets the saturation current of the optocoupler transistor. The secondary side circuit using the TL431 adjustable precision shunt regulator, is a widely used technique not specific to the PUCC3801. The 180 resistor biases the TL431 in its linear region. If the output voltage rises above the regulation point, the TL431 draws current through the optocoupler causing the voltage on COMP to fall. As the voltage on COMP falls, the duty cycle is reduced bringing the secondary voltage back to its set point. 11. Marking 8 TYPE LOT DATE TYPE LOT DATE 8 LOGO LOGO 1 03ag14 1 03ag15 TYPE: PUCC3801P LOT: Diffusion lot number (5 characters) DATE: Die revision (1 character) + Date code (yyww) TYPE: CC3801T LOT: Diffusion lot number (5 characters) DATE: Die revision (1 character) + Date code (yyww) Fig 8. Marking PUCC3801P (SOT97-1). Fig 9. Marking PUCC3801T (SOT96-1). 9397 750 08419 (c) Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 -- 10 September 2001 11 of 16 Philips Semiconductors PUCC3801 Current-mode PWM controller 12. Package outline DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1 D seating plane ME A2 A L A1 c Z e b1 wM (e 1) b2 5 MH b 8 pin 1 index E 1 4 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.14 0.068 0.045 b1 0.53 0.38 0.021 0.015 b2 1.07 0.89 0.042 0.035 c 0.36 0.23 0.014 0.009 D (1) 9.8 9.2 0.39 0.36 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 1.15 0.045 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT97-1 REFERENCES IEC 050G01 JEDEC MO-001 EIAJ SC-504-8 EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 Fig 10. SOT97-1 (DIP8) package outline. 9397 750 08419 (c) Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 -- 10 September 2001 12 of 16 Philips Semiconductors PUCC3801 Current-mode PWM controller SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE vMA Z 8 5 Q A2 pin 1 index Lp 1 e bp 4 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.014 0.0075 0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024 0.028 0.004 0.012 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 Fig 11. SOT96-1 (SO8) package outline. 9397 750 08419 (c) Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 -- 10 September 2001 13 of 16 Philips Semiconductors PUCC3801 Current-mode PWM controller 13. Revision history Table 5: 01 Revision history CPCN Description Product data; initial version Rev Date 20010910 9397 750 08419 (c) Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 -- 10 September 2001 14 of 16 Philips Semiconductors PUCC3801 Current-mode PWM controller 14. Data sheet status Data sheet status[1] Objective data Preliminary data Product status[2] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Product data Production [1] [2] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 15. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 16. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 750 08419 Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 -- 10 September 2001 15 of 16 Philips Semiconductors PUCC3801 Current-mode PWM controller Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.2 7.2.1 7.2.2 8 9 10 10.1 10.2 11 12 13 14 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Compensation pin (COMP). . . . . . . . . . . . . . . . 3 Feedback pin (FB) . . . . . . . . . . . . . . . . . . . . . . 3 Current sense input pin (CSNS) . . . . . . . . . . . . 4 Common circuit ground pin (GND) . . . . . . . . . . 4 Gate drive output pin (OUT) . . . . . . . . . . . . . . . 4 Positive supply voltage pin (VDD) . . . . . . . . . . . 4 Voltage regulator pin (REG) . . . . . . . . . . . . . . . 4 Device sections. . . . . . . . . . . . . . . . . . . . . . . . . 4 Power-up section . . . . . . . . . . . . . . . . . . . . . . . 4 Controller section . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application information. . . . . . . . . . . . . . . . . . 10 Off-line flyback regulator. . . . . . . . . . . . . . . . . 10 Optocoupler interface . . . . . . . . . . . . . . . . . . . 10 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 (c) Koninklijke Philips Electronics N.V. 2001. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 10 September 2001 Document order number: 9397 750 08419 |
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